The present invention relates to a semiconductor device, and a manufacturing method of the same, and more particularly to a technique suitable for application to a power MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a trench gate structure with a dummy gate electrode, and a manufacturing method of the same.
A patent document 1, as shown in FIG. 1, discloses a structure having a power MISFET 101 with a trench gate structure, a planar gate type MISFET 102, and a protective diode 103 formed on the same substrate. In a method of manufacturing this structure, a polycrystalline silicon film included in a gate electrode of the power MISFET 101, and a polycrystalline silicon film included in the protective diode 103 are formed independently in different steps. The thickness of the polycrystalline silicon film constituting the gate electrode is larger than that of the polycrystalline silicon film included in the protective diode 103. A source region of the power MISFET 101 and a cathode of the protective diode are formed in the same step.
A patent document 2 discloses a structure having a planar gate type power MISFET and a protective diode formed on the same substrate. In a method of manufacturing this structure, a polycrystalline silicon film included in a gate electrode of the planar gate type power MISFET and a polycrystalline silicon film included in the protective diode are formed in the same step. Also, a source region of the planar gate type power MISFET and a cathode of the protective diode are formed in the same step.
A patent document 3 discloses a power MISFET having a trench gate structure with a dummy gate electrode. In this power MISFET, the dummy gate electrode is connected to a source potential.
A patent document 4 discloses another power MISFET having a trench gate structure with a dummy gate electrode. In this power MISFET, the dummy gate electrode is connected to a positive electric potential.
A patent document 5 discloses a further power MISFET having a trench gate structure with a dummy gate electrode. In this power MISFET, the dummy gate electrode is in a floating state.    [Patent document 1] Japanese Patent Publication No. 3413569    [Patent document 2] Japanese Unexamined Patent Publication No. 2000-307109    [Patent document 3] U.S. Pat. No. 5,998,833    [Patent document 4] Japanese Unexamined Patent Publication No. Sho 63 (1988)-296282    [Patent document 5] Japanese Unexamined Patent Publication No. Hei 04 (1992)-229662